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CPU design
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#	Item
101	Simulating the Power Consumption of Large-Scale Sensor Network Applications Victor Shnayder, Mark Hempstead, Bor-rong Chen, Geoff Werner Allen, and Matt Welsh Division of Engineering and Applied Sciences Harvard Universi Add to Reading List Source URL: www.eecs.harvard.edu Language: English - Date: 2004-10-05 10:17:05 Technology Electronics Central processing unit TinyOS Sensor node NesC Microcontroller CPU design ANT Wireless sensor network Computing Embedded systems
102	VLSI DESIGN 1996, Vol. 4, No. 2, pp. i-ii (C[removed]Reprints available directly from the publisher Add to Reading List Source URL: downloads.hindawi.com Language: English - Date: 2014-05-11 09:05:38 Logic design Field-programmable gate array Hindawi Publishing Corporation CPU design Logic simulation Parallel computing Application-specific integrated circuit Digital electronics Simulation Electronic engineering Electronic design automation Integrated circuits
103	8/16-bit XMEGA A1 Microcontroller ATxmega128A1 / ATxmega64A1 Not recommended for new designs - Preliminary Add to Reading List Source URL: www.atmel.com Language: English - Date: 2014-10-13 09:34:07 Electronic engineering Central processing unit Embedded systems Instruction set architectures Atmel AVR Norwegian Institute of Technology Joint Test Action Group CPU design Instruction set Computer architecture Microcontrollers Computer hardware
104	ECE342: Computer Hardware Add to Reading List Source URL: www.ece.utoronto.ca Language: English - Date: 2014-11-28 15:23:27 Central processing unit Microprocessors Computer architecture Digital signal processing Integrated circuits Multi-core processor CPU design Very-large-scale integration Computer Electronic engineering Electronics Computer hardware
105	Exploring a Multiprocessor Design Space to Analyze the Impact of Using STT-RAM in the Memory Hierarchy A THESIS SUBMITTED TO THE FACULTY OF THE GRADUATE SCHOOL OF THE UNIVERSITY OF MINNESOTA Add to Reading List Source URL: conservancy.umn.edu Language: English - Date: 2014-12-17 15:49:56 Digital media Magnetoresistive random access memory Random-access memory CPU cache Memory hierarchy Benchmark Cell Computer memory Computer hardware Computing
106	Enforcing Memory Policy Specifications in Reconfigurable Hardware Ted Huffmire , Timothy Sherwood† , Ryan Kastner‡ , and Timothy Levin Naval Postgraduate School Add to Reading List Source URL: www.cisr.us Language: English - Date: 2009-03-04 17:17:27 Electronics Reconfigurable computing Computer engineering Field-programmable gate array Dynamic random-access memory Parallel computing Application-specific integrated circuit Bitstream CPU design Electronic engineering Computer memory Computer hardware
107	HSARPA Cyber Security R&D Add to Reading List Source URL: www.dhs.gov Language: English - Date: 2012-12-20 12:28:36 Computer memory Cache Computer architecture CPU cache CPU design Lookup table Central processing unit Computer hardware Computing
108	Contents 1 Contract Postal Unit Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1-1 Add to Reading List Source URL: www.apwu.org Language: English - Date: 2014-05-22 11:55:02 Central processing unit Contract Fixed price Business Humanities Technology Contract law United States Postal Service CPU design
109	Analyzing the Energy Efficiency of a Database Server Dimitris Tsirogiannis Stavros Harizopoulos HP Labs Palo Alto, CA, USA Add to Reading List Source URL: nms.csail.mit.edu Language: English - Date: 2010-03-20 15:49:41 Computer architecture Multi-core processor CPU cache CPU power dissipation CPU design Solid-state drive Power management Performance per watt Computer hardware Central processing unit Computing
110	Design and Evaluation of a Compiler Algorithm for Prefetching Todd C. Mowry, Monica S. Lam and Anoop Gupta Computer Systems Laboratory Stanford University, CA 94305 Add to Reading List Source URL: suif.stanford.edu Language: English - Date: 2006-06-25 21:11:32 Computer hardware Computer programming CPU cache Loop nest optimization Cache Memory hierarchy Software pipelining Lookup table Acumem SlowSpotter Computing Computer memory Compiler optimizations